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Old 10-22-2005, 07:57 AM
John McCluskey
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Default Re: Storing a file onto FPGA (the last word)

On Tue, 18 Oct 2005 14:13:54 -0400, Ray Andraka wrote:

> John McCluskey wrote:
> In principal, anything you can parse in
>>VHDL is fair game, although in practice, I've found the file IO a little
>>fragile, especially when dealing with access types. Read the XST
>>documentation to see how it's done.
>>
>>

> Cool! I didn't know that they had actually implemented it. Now if
> Synplify would follow suit, it would
> surely get filtered into the other fpgA tools over time. The write
> seemed like a logical extension, although
> I'm not sure how useful it is beyond writing a serial number or key to a
> file at compile time. Hmm, it
> may be a (albiet, kludgey) way to pass a propagation delay or latency
> back up to a higher level in the design hiearchy.


Alas, I've thought of this already, and it will only work for iterated
synthesis. If you think about it for a second, you'll realize that the
language semantics force elaboration from the top of the hierarchy down to
the bottom. Generics have to be fully calculated before the subcomponents
can be elaborated. If you have a generic parameter which depends on a
value created during elaboration of the subcomponent, then a dependency
loop will be created. This is not necessarily a bad thing, but the
programmer will have to be aware of it, and make sure to stop the
iteration of the elaboration of the subcomponent (at some point). I'd
really like to work out a design flow where this is possible, but right
now, this will require scripting a control structure to iteratively call
the synthesis tool to compile the subcomponents with specified generic
parameters. I think that right now, XST doesn't accept top level
generics as command line arguments :-(

Bottom line: It's really tough to write code that explicitly supports
multiple topologies that can automatically be explored at compile time to
close timing. VHDL needs to be extended to support design space
exploration, as well as to support physical timing feedback into the
elaboration control structures. It'll probably take the rest of the
decade to get something going with Accelera along these lines.

John McCluskey

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