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Old 10-18-2005, 08:13 PM
Ray Andraka
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Default Re: Storing a file onto FPGA (the last word)

John McCluskey wrote:

>I read this thread about initializing FPGA memory with some interest.
>Well over a year ago, I asked the XST developers in Grenoble to add
>support for File I/O during VHDL elaboration. This actually works in ISE
>7.1! You can write a VHDL function that opens a file (using the TextIO
>package), reads data out of it, and returns an array that can be used to
>initialize a signal array that has memory inferred on it. You can also
>write files, if you feel like you have a need for it. I argued that
>there exists a subclass of File I/O operations that can fit into the model
>of constant propagations that occur during elaboration. I've used this
>to write a VHDL function that will read an Intel MCS file into a ram array
>initial value during synthesis. In principal, anything you can parse in
>VHDL is fair game, although in practice, I've found the file IO a little
>fragile, especially when dealing with access types. Read the XST
>documentation to see how it's done.
>
>

Cool! I didn't know that they had actually implemented it. Now if
Synplify would follow suit, it would
surely get filtered into the other fpgA tools over time. The write
seemed like a logical extension, although
I'm not sure how useful it is beyond writing a serial number or key to a
file at compile time. Hmm, it
may be a (albiet, kludgey) way to pass a propagation delay or latency
back up to a higher level in the design hiearchy.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email [email protected]
http://www.andraka.com

"They that give up essential liberty to obtain a little
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