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Old 10-18-2005, 03:38 AM
John McCluskey
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Default Re: Storing a file onto FPGA (the last word)

I read this thread about initializing FPGA memory with some interest.
Well over a year ago, I asked the XST developers in Grenoble to add
support for File I/O during VHDL elaboration. This actually works in ISE
7.1! You can write a VHDL function that opens a file (using the TextIO
package), reads data out of it, and returns an array that can be used to
initialize a signal array that has memory inferred on it. You can also
write files, if you feel like you have a need for it. I argued that
there exists a subclass of File I/O operations that can fit into the model
of constant propagations that occur during elaboration. I've used this
to write a VHDL function that will read an Intel MCS file into a ram array
initial value during synthesis. In principal, anything you can parse in
VHDL is fair game, although in practice, I've found the file IO a little
fragile, especially when dealing with access types. Read the XST
documentation to see how it's done.

I have various nefarious plans for this capability, particularly in the
area of automatically iterated code that refashions the circuit topology
to deal with the timing failures found on the previous iteration.

Bottom line... you can read and write files during VHDL synthesis with
XST. I've heard some talk about Verilog 2001 being used for much the
same thing, but don't know if it works yet.

I'm not satisfied with synthesis File I/O in VHDL... I'd much rather have
the ability in VHDL to control synthesis iteration on sub-components that
fail to meet timing. But that's an argument I'm saving for the VHDL-200X
committee.

John


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