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Old 10-18-2005, 12:30 AM
Ray Andraka
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Default Re: Storing a file onto FPGA


>> In principle there is nothing that prevents the synthesis tools to
>> execute processes that are only activated once to determine the
>> result.

>
> I agree to that.
> As long as we are discussing the above problem of initializing RAMS/ROMS
> from files this would be a nice feature for the next VHDL Standard.


You can already to this in synthesizable VHDL using functions. The
difficulties come in from trying to read data from a file, and when
working with real numbers. Both of these already exist in VHDL. The
problem isn't a VHDL standards problem, rather it is due to the
synthesis tools not recognizing the functions in stdio/textio and
math_real. This is understandable since neither are synthesizable, but
they could in principle be allowed in functions only for sythesizable
code...ie for generation of constants. I do recall a while back that
synplicity indicated that they would start allowing reals for developing
constants. I don't know that it actually came to pass, as I haven't
tried that in a number of years, as it is not generally recognized by
simulators. If you want this capability to be supported in your tools,
then let the synthesizer vendors know your wishes. This doesn't require
any changes to VHDL as a language or any new constructs, just limited
added support in the synthesis tools to allow file i/o and computation
using reals in a limited set of circumstances (ie, in functions where
the computation or file read results in constants).



--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email [email protected]
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759


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