View Single Post
  #16 (permalink)  
Old 10-17-2005, 08:32 AM
Posts: n/a
Default Re: Storing a file onto FPGA

Hi Kolja
Kolja Sulimma schrieb:
> backhus wrote:
>> Hi Robert, your first idea appears often in a designers mind,
>> because it works so well in simulation. But in synthesis the tool
>> is not executing your code, only analyzing it and looking for
>> synthesizable parts. The rest of the code will be ignored in the
>> best case or gives you errors and warnings.

> Actually the synthesis tools execute some of your code: Expressions
> are evalutated, for and generate loops unrolled, etc.

I see a difference between execution and evaluation.
- execution is taking input values and producing outputs.
- evaluating is calculating the right connections (and logic etc.)
between inputs and outputs.
(There are probably more accurate definitions available)

> In principle there is nothing that prevents the synthesis tools to
> execute processes that are only activated once to determine the
> result.

I agree to that.
As long as we are discussing the above problem of initializing RAMS/ROMS
from files this would be a nice feature for the next VHDL Standard.

> Also, logic that converts text to integers can be described by an rtl
> netlist and with a little luck redundancy removal will boil it down
> to a lookup table.

RTL... Please dont!
I'd rather like an evaluation of a static expression (I hope I said
this right) which costs no hardware.
If format conversion would actually create (and use) logic elements ,
guess what will happen: Thousands of beginners will post questions like
"I have created a bunch of counters with integers and the tool
synthesizes them to a million gates..." :-)

Also: If you create actual logic for converting the contents of a file
to some binary representation which will be executed at runtime of the
chip how will you provide access to that file? Imagine the consequences,
and if that really is what designers are asking for.

> Opening files can be handled similar to an "include" statement.

For initialisation purposes I would welcome it.

> But this will not happen before a flip-flop with enable can be
> written as: if rising_edge(clk) and enable='1' then .... which still
> is not understood by most synthesis tools.

Especially cheap/free tools from chipvendors. I think Synopsys, Mentor
or Cadence tools will understand it and create the right logic for every
target architecture.
Limiting tools to a style dependant subset may be somewhat annoying,
because it affects the tool independance of the source code, but then if
only full lrm-compliant synthesis tools would be allowed, could any
company give them away for free. It's a matter of money her.

> At last years GI workshop there was a paper that used XML/XSLT to
> convert a load of "unsynthesisable" VHDL constructs into code that
> even XST considers to be synthesizable. Most of these transformations
> were really simple. Apparently the tool vendors settled years ago on
> what should be synthesizable and what shouldn't and now are too lazy
> to push that border.

I confess, I don't know this paper.
But have you taken a look at the synthesizable sources created by these
tools (I assume they are creating VHDL as an output in the end) ?
Would it really be so hard to write in that codestyle for yourself?
How about the synthesized results? Synthesizable is not always identical
to useable.
Maybe the sources will become more elegant to read...
Can you provide a link to that paper. It's an interesting topic.

In conclusion I might say that VHDL is under continuous development,
which unfortunately is a very slow process.

Reply With Quote