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Old 10-15-2005, 05:58 PM
Kolja Sulimma
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Default Re: Storing a file onto FPGA

backhus wrote:
> Hi Robert,
> your first idea appears often in a designers mind, because it works so
> well in simulation. But in synthesis the tool is not executing your
> code, only analyzing it and looking for synthesizable parts. The rest of
> the code will be ignored in the best case or gives you errors and warnings.


Actually the synthesis tools execute some of your code: Expressions are evalutated,
for and generate loops unrolled, etc.
In principle there is nothing that prevents the synthesis tools to execute processes
that are only activated once to determine the result.

Also, logic that converts text to integers can be described by an rtl netlist and with
a little luck redundancy removal will boil it down to a lookup table. Opening files
can be handled similar to an "include" statement.

But this will not happen before a flip-flop with enable can be written as:
if rising_edge(clk) and enable='1' then ....
which still is not understood by most synthesis tools.

At last years GI workshop there was a paper that used XML/XSLT to convert a load of
"unsynthesisable" VHDL constructs into code that even XST considers to be synthesizable.
Most of these transformations were really simple. Apparently the tool vendors settled
years ago on what should be synthesizable and what shouldn't and now are too lazy to
push that border.

Kolja Sulimma
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