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Old 10-15-2005, 02:18 AM
Ray Andraka
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Default Re: Storing a file onto FPGA

Philip Freidin wrote:

>On 13 Oct 2005 11:39:06 -0700, "Robert" <[email protected]> wrote:
>
>
>>^Thanks!
>>Also, when you say cutting and pasting into VHDL code, do you mean that
>>I'll have to do this each time the data in my txt file changes?
>>
>>

>
>The answer to this would typically be yes.
>
>
>
>>The
>>data I generate in the text file will change depending on my inputs. I
>>need a way so that I can quickly load/initialize the RAM with the new
>>values from txt file.
>>
>>

>
>I'm confused by this. In your earlier post, you said that the
>text file was created by a Python program. You then wanted a
>way to take this text, and encode it somehow and have it included
>in the bitstream that configures the FPGA. There are many ways to
>do this, and some have been described by other posters to your
>question.
>
>By "inputs" do you mean signals to your FPGA, or parameters to
>your Python program?
>
>If there is a small set of inputs, then I guess you could build
>them all and load them all into the FPGA (needs N x memory), and
>select at runtime what you need. If the parameters are unbounded,
>then you need a more complex process, since this implies running
>Python for each change in the inputs.
>
>
>
>>Thanks in advance.
>>Robert.
>>
>>

>
>Ray pointed out that a cut-and-paste process can be used to get
>from a text file to a block of VHDL/Verilog initializer statements,
>or with Xilinx's data2mem program. If you find yourself going down
>this path, I highly recommend that use an editor program that
>includes a "column edit" mode, and maybe also a hex mode. My
>favorite editor is UltraEdit, that is reasonably cheap, and an
>excellent programmer's editor.
>
>
>Philip
>
>
>
>
>Philip Freidin
>Fliptronics
>
>

If this is something you are going to be changing several times, it
might not be unreasonable to write a translator that takes your text
input and outputs a VHDL package containing the memory contents as a
constant array. I've done that both in 'C" and in Matlab, as well as in
non-synthesizable VHDL. The file containing the package just gets
included with the rest of the files at design time. That way, you don't
have to touch any of your design files, just one file containing a
package that has your data in it. You can also generate the data file
in the Xilinx .coe file format and load the data into the memories at
compile time.



--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email [email protected]
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759




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