^Thanks Philip and Eilhert.

A clarification for Philip:
I need to generate different data files using Python scipts and then
want to store this on the FPGA. The inputs I was talking about was for
the python, which will generate different output data files each time.
I am not sure if it would be possible to store all of the possible data
file outputs from Python onto the FPGA. Consequently, cut-paste won't
be a very good option here.

For general audience:

I just found out there in Altera, its possible to define your data into
a very simple memory format (addresses and data). This file can then be
used to intialize the RAM/ROM on to the FPGA.

I am quite sure it can be done on Xilinx as well. But I am don't know
how to do it. Can somebody show steps as to how to initialize the
memory? Obviously, sample codes are not that easy to find.

Robert.