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Old 10-14-2005, 08:16 AM
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Default Re: Storing a file onto FPGA

Hi Robert,
your first idea appears often in a designers mind, because it works so
well in simulation. But in synthesis the tool is not executing your
code, only analyzing it and looking for synthesizable parts. The rest of
the code will be ignored in the best case or gives you errors and warnings.

If you want to develop FPGAs with certain RAM contents defined by some
other tool before synthesis you better try this flow:
- develop your design assuming that your RAM/ROM contents are available
after startup.
- after PAR extract the paths to your memeory elements e.g. by using the
floorplanner tool (maybe there are other ways too).
- write a BMM file (even if XILINX still makes a big secret of the
syntax. :-) Read some examples, that helps.)
- use the data2mem tool to patch your bitstreams with the actual memory
contents generated by your special tool or script (provide the correct
file format for data2mem)

For Simulation, if you are using modelsim 6.xx, you can work similar to
the above flow.
-Load your design and your testbench into vsim.
- use the mem load command to initialize the memory elements in your
design (you can find out about the correct file syntax by filling some
pattern directly into your memory with mem load and then storing it with
mem save)

This way you don't need to use your HDLs file io anymore inside your
design and have similar flows for synthesis and simulation.

have a nice synthesis

Robert wrote:
>I am writing a verilog code whereby I read data from a txt file and use
>it in one of the modules. I want to store the data from the .txt file
>on to FPGA, where it can be used by other modules.

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