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Old 10-13-2005, 07:58 PM
Ray Andraka
Posts: n/a
Default Re: Storing a file onto FPGA

Robert wrote:

>Thanks for the reply.
>The txt file I am planning to use contains some video packets, which
>are generated by a set of Python scripts. Writing verilog modules to
>generate the data in the txt file would be to start all over again,
>which I think is unnecessary. I was hoping that there would be some
>short cut way by which you can initialize the memory on the FPGA or may
>be define the memory on FPGA.
>How do people store long look up tables on FPGA? Especially if the
>look-up table data... let's say coefficients for something... are
>generated by some other program.

You could declare the text as a string constant in VHDL, then write a
vhdl function to convert the text into the bit vector data needed to
initialize the BRAM. I do a similar thing for some of the tables in my
DSP design, where I generate the table and convert it to integers using
Excel, then cut and paste the column from Excel into a VHDL integer
array constant. The cut an paste for an integer array is easier if you
put a column of commas in the column to the right of the column of
integers in the excel spread sheet, and then copy both those columns to
the VHDL. Likewise, you can also use matlab to generate a table of
integers, writing it to a file using DLMwrite, and then opening that
file with a text editor and cutting and pasting into your vhdl editor.

In the case of the string, you'll have to write your own function to
convert the string characters to integers if you do it in VHDL because
the synthesis tools do not recognize the textio package. It isn't hard,
just tedious.

--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email [email protected]

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

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