Version 5.0 of QUIP is now on the web. If you're researching FPGA CAD,
architecture or applications, or you're teaching a graduate-level CAD
course, the hooks into the Quartus CAD system described here are likely of
interest. See
https://www.altera.com/support/softw...p-download.jsp
to download.

Major new features in this release are:

- Detailed device documentation for the Stratix II and Cyclone II
architectures, enabling researchers to write CAD tools targeting these
architectures
- Ability to write blif files out of Quartus, enabling the use of Quartus as
an RTL front-end to get HDL benchmarks to academic synthesis tools (see
documents/quip_synthesis_interface.pdf)
- A set of benchmark circuits, including several containing over 30,000 LEs,
some with DSP blocks, and many with memory (see
documents/quip_benchmarks.pdf)
- A description of how to set the Quartus optimization goals and measure the
relevant parameters so that you can fairly and accurately compare an
academic CAD tool to Quartus (see documents/quip_benchmarking.pdf).

Feel free to contact me if you have any questions or suggestions, or if you
have benchmark circuits to contribute to the FPGA research community.

Regards,

Vaughn Betz
Altera
[v b e t z (at) altera.com]