Brad,

There are so many ways of doing this, depending on your FPGA family,
required timing and the available resouces, but other than using the
"natural resources", simple LUTs, pipelines, even multipliers, etc., you can
also use memories. Personally, I like using memories for state machines,
especially for channelized state machines or LUT for pre-computed CRC
calculation.

If we are talking about Virtex family, we have 16384 bits RAMs, which can be
used as 4096x4 LUT, where you have a '1's counter within 12-bit vector,
which is applied as an address of the entry. Each entry holds the number of
'1's. It is clear how to expand this concept further to any vector,
depending on the timing requirements and the available resources.

One way is that you can try 5 memory blocks like this and it will give you
60 bits covered, then simply add the "data_out"s and the extra bits and
pipeline them.
There could be more "balanced" or optimal usage of memories and FFs.

I hope i did not make any math mistake here.

Vladislav



"Brad Smallridge" <[email protected]> wrote in message
news:[email protected]...
> Hello Group,
>
> What is the best way to count 64 incoming simultaneous
> bit signals to determine the number of 1s (in VHDL)?
> I have clock cycles to spare but the result must be pipelined
> so that each clock cycle produces a new count.
>
> Brad Smallridge
> b r a d @ a i v i s i o n . c o m
>
>
>