Ones Count 64 bit on Xilinx in VHDL
Hello Group,
What is the best way to count 64 incoming simultaneous
bit signals to determine the number of 1s (in VHDL)?
I have clock cycles to spare but the result must be pipelined
so that each clock cycle produces a new count.
Brad Smallridge
b r a d @ a i v i s i o n . c o m
|