Paul Solomon wrote:

> I am using a straix part and it is clocked at 80MHz, and I have a number of
> FIR filters in the design. There are currently 2 FIR filters that need to
> run at 80MSPS and then a seriec of filters that these feed into after
> decimation, so these other filters run a lower clock rates.

Consider running everything at 80MHz and use
clock enable inputs where needed for lower
effective rates.

-- Mike Treseler