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Old 03-30-2005, 07:24 AM
Johan Bernspång
Posts: n/a
Default Re: Dividing a 24 bit std_logic_vector by a decimal number

genlock wrote:

> Can you explain this logic that you have mentioned in more detail?
> I am using Xilinx ISE and when I try doing any division or
> multiplication, it keeps showing an error as follows:
> / can not have such operands in this context.
> ERROR: XST failed
> a)What I am trying to do is first convert the 24 bit vector to an
> integer.
> b)Then figure out a method to divide this integer by 1.36 that gives
> the result as an integer
> c)This integer is converted back to a 24 bit vector
> Any idea about how this division (b)can be performed?
> Thankyou

If you're using ISE you can always have a look into the Language
Templates (the icon with the light bulb on it).

The following code will do the trick:

signal product : std_logic_vector(47 downto 0);
signal mult_in : std_logic_vector(23 downto 0);
constant const_val : std_logic_vector(23 downto 0) := X"the divisor";

process (clk)
if rising_edge(clk) then
product <= mult_in * const_val;
end if;
end process;

To make sure you're inferring hardware multipliers you have to set the
correct synthesize properties for that.

The value of the perfect constant could probably be a discussion in
itself but I would probably multiply by 47 (i.e. 2F hex) and then do a 6
bit right shift after the multiplication:

prod_out <= product(41 downto 18);

This method does not divide exactly by 1.36, but pretty close: 1.362.

Correct me if I'm totally wrong...

Johan Bernspång, [email protected]
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

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