I'm a Verilog guy and your question is for VHDL - it would be great if a

VHDL guy gould give the proper code snippets. The question is addressed in

general:

"genlock" <

[email protected]> wrote in message

news:

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> Yes the decimal number is a constant value.
For the example of division by 1.36, multiplying by (2^24/1.36) and taking

the 24 MSbits of the result, you get an "effective" division. If you

generate the "reciprical integer multiplier" from real literals and do a

type conversion to std_logic_vector, the multiply would follow as a simple

multiply. Then just shift or select the upper bits and you have your

result.

> What do you mean by embedded multipliers?
The modern FPGAs tend to have multipliers as part of the logic fabric.

You're using ISE so my expectation is you're using a

Virtex(-E)Virtex-II(Pro), Virtex-4, Spartan-II(E), or Spartan-3/3L/3E.

These should all have multipliers if memory serves me right. Check the data

sheets.

> Is there a VHDL code available for that or how do we go about coding

> one.
I'd like to see someone on this newsgroup provide you a snippet to do

(roughly) what I suggest. If you wanted Verilog, it'd be something like

result[23:0] <= In[23:0] * ((1<<24)/1.36 + 0.5) >> 24;

but I haven't used real variables in my code much if at all. I think this

would synthesize.

> I dont need a clock for this one.

>

> Thankyou