View Single Post
  #2 (permalink)  
Old 03-29-2005, 08:08 PM
Posts: n/a
Default Re: Dividing a 24 bit std_logic_vector by a decimal number

First of all, is the decimal number constant?
If so, think multiplication. Embedded multipliers are quick and easy while
dividers are much more work.

Do you need a new result every 200 MHz clock or do you need to know the once
every 3 microseconds?

"genlock" <[email protected]> wrote in message
news:[email protected]
> Hi,
> Is there anywayz a 24 bit std_logic_vector can be divided by a decimal
> number (eg: 1.36)using VHDL.
> The quotient needs to be a 24 bit std_logic_vector as well.
> I am currently using Xilinx ISE for implementing this division.
> Any help is appreciated.
> Thanks

Reply With Quote