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Old 03-29-2005, 07:43 PM
genlock
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Default Dividing a 24 bit std_logic_vector by a decimal number

Hi,
Is there anywayz a 24 bit std_logic_vector can be divided by a decimal
number (eg: 1.36)using VHDL.

The quotient needs to be a 24 bit std_logic_vector as well.

I am currently using Xilinx ISE for implementing this division.

Any help is appreciated.

Thanks

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