Dividing a 24 bit std_logic_vector by a decimal number
Hi,
Is there anywayz a 24 bit std_logic_vector can be divided by a decimal
number (eg: 1.36)using VHDL.
The quotient needs to be a 24 bit std_logic_vector as well.
I am currently using Xilinx ISE for implementing this division.
Any help is appreciated.
Thanks
