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Old 02-21-2005, 05:30 PM
Posts: n/a
Default Re: Issues with a batch of Virtex-II chips

> Have you re-run timing analysis on the 5.3 design, but using the latest
> timing analyser and latest speed files?

No, because I don't think there's any timing issue here. The logic is
trivial and runs at low speed. We are using the same "clock generation"
module in several other designs, without any issues. We have products
running 24/7 for two years now without a single issue. As I stated before,
the problem appeared only with the selected chips.

But, I will test our new Virtex-II designs with the latest timing analyzer
and latest speed files as you suggested. It's a good idea for new designs.

> With 6.1, have you tried MPPR (multi-pass pacement and routing)?
> Sometimes modifying the placement (in FPGA editor) of failing paths and
> re-running "re-entrant routing" can fix problems, if there are only a
> small number of failing paths.

Yes, I have. I tried 6.1, 6.2 and 6.3. It's always the same story.
Placer/Router does a lousy job. Either the constraints can't be met or the
router can't connect all the nets. ISE 5.2 SP3 completes without any errors
and reports 7 logic levels for the constraint. On the other hand ISE 6.x
reports 16 logic levels for the same constraint.

In my experience (for the Virtex-II family) if the design takes less than
~90% of chip resources then the results of ISE 6.x are similar to the ISE
5.2 SP3, sometimes even better, but as soon as design takes more than 95% of
all chip resources then ISE 6.x gives up. Similarly I still use ISE 3.3 for
SpartanXL and Spartan2 designs, because ISE 4.2 or newer don't produce the
desired results. I know a lot depends on the synthesis tool (I'm using

Thanks for you suggestions,
Igor Bizjak

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