I made a mistake shift register is :
> data_reg <= data_in & data_reg(14 downto 0) ;
> data_out <= data_reg(0);


"KCL" <[email protected]> a écrit dans le message de news:
[email protected]...
> thanks for note
>
>
> 1) integer count : usually i use std_logic for all my signal and use
> conversion function for arithmetic, so i have no problem of wrap around,
>
> 2) reset missing : does at startup all signal have a value unknow but
> equal to '1' or '0' so after max 16cycles cpt should back to 0 so there
> is a 16 cycle clock intial time that (depend of your application need but
> in most of DSP) is not important I think.
>
> Also for reset what is the best synchronous or asynchronous?? because
> synchronous reset seems to need less ressource??
>
> 3)not a shift register but i think this not a real shift register he
> wanted :"parallel in serial out latching shift register" for me he asked
> for serializator (sorry my english is so bad so I translate as I can)
> if i wanted to do a shift register i will have done:
>
>
> data_reg <= data_reg(14 downto 0) & data_in;
> data_out <= data_reg(0);
>
> Finally I just will add that still people not explain very well what they
> wanted , we couldn't give them exactely what they want to do (and also
> that they could search by themself , it 's not not too bad for brain
> activity)
> And excuse me for my "errors" but I just notice that only a french guy
> with only 6month internship in VHDL developpement(and limited english
> comprehension) take time to answer to his problem.
>
> Regards
>
> Alexis
>
> "Christian Schneider" <[email protected]> a écrit dans le
> message de news: [email protected]...
>> Well, there are some issues with this code example:
>>
>> 1) The reset is missing, this is a problem for the simulation
>>
>> 2) integer based counters tend to not wrap arount automatically, I do not
>> know for sure what synthesis might result, but simulation will fail
>>
>> 3) While the general behavior is ok with the above points corrected, this
>> is not a shift register. Sorry. See notes below.
>>
>> Try again!
>> Chris
>>
>>
>> KCL wrote:
>>> probably something like
>>> ---------------------------------
>>> signal cpt : integer range 0 to 15; --i'm not sure for this declaration
>> this is ok
>>
>>> usually i use only std_logic with convertion
>>> signal temp : std_logic_vector( 15 downto 0);
>>>
>>> process(clk)
>>> begin
>>
>> Missing reset here, initialize cpt here!
>>
>>> if rising_edge(clk) then
>>> cpt <= cpt +1 ;
>> This is a counter which does not wrap around, since it is of type
>> integer! Take care!
>>
>>> if cpt = 0 then
>>> temp <= in_parallel;
>>> end if;
>> Parallel loadable register. ok.
>>
>>> out_serie <= temp(cpt);
>> Multiplexer, with output register. NOT a shift register!! Where is the
>> shift??
>>
>>> end if;
>>> end process;
>>> ----------------------------------------
>>>
>>>
>>> there is many others way to do it you just have to test different
>>> solution to get the better and have imagination...
>>>
>>> alexis
>>>
>>> "bob" <[email protected]> a écrit dans le message de news:
>>> [email protected]...
>>>
>>>>Shift register example?
>>>>Hi I am looking for a parallel in serial out latching shift register
>>>>in VHDL.
>>>>I want 16 bits but any example would be appreciated.
>>>>
>>>>Thanks
>>>>
>>>
>>>
>