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Old 02-20-2005, 02:10 PM
Brian Drummond
Posts: n/a
Default Re: Issues with a batch of Virtex-II chips

On Fri, 18 Feb 2005 21:55:42 +0100, "IgI" <[email protected]> wrote:

>I'm using Virtex-II (XC2V1000-FF896-4C) in one of the product which we have
>been selling for over 3 years. Recently we got "new" batch of Virtex-II
>chips and problems started to arise.
>PCBs with chips from batch B and C are working fine, on the other hand none
>of the 42 PCBs, where chips from batch A are used are working.
>We are currently using ISE 5.2 SP3 for this design. I have verified the bit
>stream by reading it back from the chip and it's ok.
> I
>can't use ISE 6.1 or newer because the routing is not successful or ISE
>simply doesn't meet the timing constraints (the chip is 99% full).

Have you re-run timing analysis on the 5.3 design, but using the latest
timing analyser and latest speed files?

Sometimes the speed files are changed to reflect new information about
the devices ... usually in the "right" direction. But if the old
(formerly successful) design fails with new speed files, that might
point you towards a solution.

With 6.1, have you tried MPPR (multi-pass pacement and routing)?
Sometimes modifying the placement (in FPGA editor) of failing paths and
re-running "re-entrant routing" can fix problems, if there are only a
small number of failing paths.

- Brian
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