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Old 02-19-2005, 06:26 AM
IgI
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Default Re: Issues with a batch of Virtex-II chips

> ( I assume that you are not using any DCM outputs for input clock less
than
> 24 MHz)


10MHz clock is generated externally.

> So this problem was resolved by defining a reset registers for each PLL,

and
> asserting/deasserting the reset by the software (or some delay implemented
> in FPGA by some large counter) in chain.


Each DCM has it's own reset line connected to reset register and is
asserted/deasserted by software.

Thanks for sharing you experience,
Igor Bizjak




> I assume this is this is different from what you've experienced, but hope
> this helps.
>
> Sincerely,
>
>
>
> Vladislav Muravin
>
> Senior FPGA Design Engineer
>
> Advantech AMT (Advanced Microwave Technologies)
>
> 657 Orly Avenue
>
> Dorval H9P 1G1
>
> Quebec, Canada
>
> Tel: (514) 420-0045 ext. 240
>
> Fax: (514) 420-0073
>
> http://www.advantechamt.com
>
>
>
>
>
> Finally, i noted that
>
> "IgI" <[email protected]> wrote in message
> news:[email protected]
> > Hi!
> >
> > I'm using Virtex-II (XC2V1000-FF896-4C) in one of the product which we

> have
> > been selling for over 3 years. Recently we got "new" batch of Virtex-II
> > chips and problems started to arise. So far I have isolated PCBs with

> three
> > different batch of Virtex-II chips:
> >
> > Batch A:
> > XC2V1000
> > FF896AFT0301
> > F1247582A
> > 4C
> > Philippines
> >
> > Batch B:
> > XC2V1000
> > FF896AGT0409
> > D2169507A
> > 4C
> > Taiwan
> >
> > Batch C:
> > XC2V1000
> > FF896AFT0205
> > F1205613A
> > 4C
> > Philippines
> >
> > All the chips in batch A have the suffix AFT301, all the chips in batch

B
> > have the suffix AGT0409,...
> > PCBs with chips from batch B and C are working fine, on the other hand

> none
> > of the 42 PCBs, where chips from batch A are used are working. PCBs are

> the
> > same (same revision) for all the products, all other components

(ZBTRAMs,
> > DDR SDRAMS, passive components,....) are the same. All voltages are with

in
> > the safe margins, all input clocks are clean. All the affected boards

pass
> > the JTAG test, in other words we didn't find any soldering errors, short
> > circuits, vias without metallization, wrong resistors or capacitors,
> > incorrectly oriented diodes or capacitors... or any other error we could
> > think of. We got all the chips in a sealed package. PCBs were tested at
> > different temperatures (from 8 degrees Celsius to 46). Only the PCBs

with
> > chips from batch A don't work. Let me explain what precisely is not

> working.
> >
> > I'm using 6 DCMs to generate clocks for ZBTRAM, DDR, System,

> ConfigBus,...
> > and two DCMs don't set the locked signal after I release them

sequentially
> > from reset. I don't know if other parts of the design (the parts which

> don't
> > use ZBTRAM clock) don't work either, because the missing clock is a

fatal
> > error and I didn't have the time to investigate further in that

direction.
> > Working freq. of ZBTRAM is 120MHz, DDR is working at 166MHz, System at
> > 100MHz, ConfigBus at 10MHz,...
> >
> > We are currently using ISE 5.2 SP3 for this design. I have verified the

> bit
> > stream by reading it back from the chip and it's ok.
> > Two coworkers, guys from the production and I are working on solving

this
> > problem for the last two days and we are almost out of ideas what else

we
> > could try, except replace the problematic chips with the

non-problematic.
> I
> > can't use ISE 6.1 or newer because the routing is not successful or ISE
> > simply doesn't meet the timing constraints (the chip is 99% full).
> >
> > Have you experienced anything similar in the past? How did you solve the
> > problem? Do you have any ideas/suggestions what else I could try? I

> couldn't
> > find any document on the xilinx web site explaining the detailed chip
> > signatures. I would like to know, what AFT0301 stands for? Is this the
> > product date, production line, factory code...? I would like to know,

when
> > the chips have been manufactured (how old are they)?
> >
> > I guess we'll have a competition in the company next week. And the goal

> will
> > be; who can throw virtex-II the farthest... Ok, I'm just joking, but I
> > needed to vent...argh...
> >
> >
> > Igor Bizjak
> >
> >

>
>



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