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Old 01-18-2005, 07:10 PM
glen herrmannsfeldt
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Default Re: Problems in timing simulations

michel leconte wrote:

(snip)

> My design has been P&R for two frequencies : 50 MHz and 80MHz.


> In this two cases, the timing report indicates no errors
> and all the timing constraints were achieved.


(snip)

> But at timing simulation, some differences appear.
> At the lower frequency, the design responds well to the stimuli and
> they were no warnings.


> At 80 MHz, after my reset phasis, I see two kinds of warnings :


> 1. X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK
> 2. X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK


(snip)

Setup time is how long the signal must be stable before the CLK
edge, hold time is how long it must be stable after. Either can
be negative but the sum must be positive.

Setup violations can occur from running a design at too high a
clock rate, but normally not hold violations. (That is, for a
synchronous design with one clock.)

As others have indicated, it is likely that you are violating
the constraints on the input. If your logic family doesn't have
zero hold time, you can't change the logic inputs on the clock
edge. Easiest is to change them on the opposite clock edge to
the one used by the FFs.

-- glen

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