Matt,

The Ml300 also supplies a 156.25 differential clock, but if that gives
problems, the direct diff clock at 125 MHz would indeed be a step in
the right direction. Thanks for the info!

Tony

On Fri, 2 Apr 2004 12:36:32 -0500 (EST), Matthew E Rosenthal
<[email protected]> wrote:

>Tony,
>I used a HW gmac core on the ml300. I believe we used a differential
>clock input (62.5 *2 ) = 125 Mhz. Maybe you can use this clock instead.
>This signal is provided on the ml300 board. i dont have the docs in front of me
>but I belive it comes in on either pins B13,C13 or B14,C14
>
>My other experience with gmac core and corresponding reference designs are
>VERY bad at best, and xilinx support in that area is no better.
>maybe using the gig ports with the PPC is a little better but...
>
>Matt
>
>On Fri, 2 Apr 2004, Tony wrote:
>
>> I am curious if anyone here has had success maintaining a very low BER
>> link using the fiber connections on the ML300 boards.
>>
>> We have implemented an Aurora Protocol PLB Core for the ML300 (adding
>> interface FIFO and FSMs to the Aurora CoreGen v2 core. It is
>> currently a single lane system using Gige-0 on the ml300 board (MGT
>> X3Y1). We were having small issues using the 156.25 bref clock so we
>> are currently using a 100 MHz clock (we are just using the PLB clock
>> plb_clk out of the Clock0 module on the EDK2 reference system). Clock
>> compensation occurs at about 2500 reference clocks. (tried 5000, same,
>> if not worse problems). Best results were with Diffswing=800mv,
>> Pre-Em=33%.
>>
>> Unfortunately our link has problems staying up for more than 20
>> minutes (it will spontaneously lose link and channel, until a
>> mgt-reset on both partners kicks them off again). Additionally, there
>> are mass HARD and SOFT errors reported by the Aurora core. I do not
>> send any data, just let the Aurora core auto-idle. This is the
>> timing:
>>
>> DIFFSW=800 PREEM=33% Stays up: 30+ minutes, ~5 soft errors/sec
>> DIFFSW=700 PREEM=33% Stays up: 30+ minutes, ~10 soft errors/sec
>> DIFFSW=600 PREEM=33% Stays up: not tested, ~20 soft errors/sec
>> (explodes to 200-300 errors/sec at about 13 minutes)
>> DIFFSW=500 PREEM=33% Stays up: not tested, ~30 soft errors/sec
>> (explodes to 200-300 errors/sec at about 13 minutes)
>>
>> DIFFSW=800 PREEM=25% Stays up: not testeds, ~200-300 soft errors/sec
>>
>> - In loopback mode (serial or parallel) the channel/lane are crisp and
>> clean as ever.
>>
>> - When the boards start up, the errors in each situation are small
>> parts/second, but then grow over time. I dont know if this is a
>> function of board/chip temperature (i put a heat sink on and it seems
>> to slow the increase of the error rate), or if for some reason the
>> Aurora core cannot compensate for some clock skew and jitter
>>
>> -
>>
>>
>> Could any of you guys steer me in the right direction?
>>
>> Is the higher loaded plb_clk as my ref_clk a source of problem?
>> Anybody able to get low error rates?
>>
>> Thanks,
>> Tony
>>
>>
>>
>>
>>
>>
>>