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Old 01-23-2004, 10:32 PM
Ray Andraka
Posts: n/a
Default Re: is this a good idea

The global reset nets in FPGAs are generally too slow to use in systems that are using the clock rate
capability of the FPGA. In those cases, you need to assume the reset is asynchronous to your clock
anyway because the propagation time on the net can exceed the clock cycle making its release
indeterminate relative to the clock, and possibly on different clock cycles in different places on the
design. All that really needs to be reset is critical circuits on the FPGA. For the most part, this
means you just need something to force any feedback loops to a known state so that after some known
number of cycles with reset asserted, you know the state of all the registers in the design without
having to do an explicit reset on more than a small portion of the design. FPGAs do come out of
configuration in a known state, however you should hold the reset on critical items like state machines
for a clock or two to make sure everything starts cleanly. Sometimes, even that is unnecessary other
than for simulation purposes if you have a state machine with no illegal states, for example a counter
that only needs to produce an output at some interval for which you do not care about the phasing.

Assaf Sarfati wrote:

> [email protected] (Paul) wrote in message news:<[email protected] com>...
> > Hi
> >
> > I know that the "reg"'s are all zeroes when powered on (on Xilinx
> > FPGAs). Is this a good idea (assumption) to work on? Can I assume the
> > same for ASIC development? that is I don't have to change my codes
> > later on?
> >
> > Thanks.

> This is a very bad idea. Bad/no design for exiting reset state will
> cause your ASIC/FPGA to be unreliable - sometimes it will start
> working, sometimes not.
> In addition, most simulators HATE it - they will start with everything
> in "unknown" state. Reset-recovery problems are very hard to simulate
> (same category as meta-stability problems - not really deterministic),
> so that the design appears to be OK in simulation.
> Best practice:
> * EVERY flip-flop should be explicitly reset (including FFs in I/O
> pads).
> * Resets are global nets, treated exactly like clocks. Most FPGAs
> allow using dedicated clock nets for reset - recommended.
> * Each clock-domain should have its own reset. The trailing edge of
> the reset signal should be synchronous to the clock and shouldn't
> violate reset-recovery timing for any FF. (use a synchronizer for
> reset - the probability of two FFs stuck in meta-stable state is much
> lower than one or two of a set including tens of thousands FFs in the
> clock-domain).
> * Just to make your design clear, use the same signal-name everywhere
> for every reset net (also good practice for clock nets).

--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email [email protected]

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

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