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Old 01-21-2004, 01:16 PM
John Adair
Posts: n/a
Default Re: Xilinx design process....

There is lots of stuff to have a look at try here for starters . The Xilinx tools usually have documentation with
them and/or web linked help. There are also free Webpack tools on the Xilinx
site should you want to update to recent software. These tools should take
edif input or you can do VHDL or Verilog design if you prefer.

If you look in the "libraries guide" from Xilinx you will find a list of
macros (elements) and what product families support them.

If your Orcad suite doesn't support simulation the easiest path to simulate
is usually generate a VHDL or Verilog netlist which most simulators support.
There are a number of ways to do this but one way is use Webpack's "Generate
Post-Fit Simulation Model". Some simulators will also import or compile edif
directly. If you want to go through this in more detail please contact me as
listed on our website.

John Adair
Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.

"David Collier" <[email protected]> wrote in message
news:[email protected]
> OK. I tied asking some of this stuff before, but didn't seem to get any
> full answers... so I'll try to revisit.
> If there's a Xilinx-support-site or system I should be using instead, then
> do, please, refer me to it.
> I'm messing about with 9536 and friends. Real simple PLD stuff.
> Xilinx/Cadence supplied a sort of library of "things" which could be used
> to make up 9536 circuits in Orcad. It puzzled the hell out of me, because
> some of them would compile for the 9536, and some wouldn't. After much
> reading, I've separated it into 2 libraries. One is basic primitives which
> work on all Xilinx PLDs, the other is macros which work on the 95xx
> family. I had to fillet out and dump those objects which were for other
> PLD series, but I think I'm there now.
> If anyone wants the OrCAD libs, email me as davidc at Dexdyne dawt com
> So I can draw Orcad ccts, create edif files, plug the edif into the
> project in the ISE, and program my devices by JTAG. All pretty slick.
> But I haven't an idea in hell how to simulate the thing. I've used the
> Altera IDE, where there is a nice simple simulator, and it's all part of
> the IDE, and it took me a very short time to get to grips with. But Xilinx
> seems to have decided not to write their own, but bundle someone else's.
> I understand I have to put the results into the ModelSim stuff, which
> seems to be capable of doing way more complex things than I'm every going
> to try this year, but it is very fierce fo9r a newbie to try to use on a
> simple 36 cell PLD.
> It doesn't seem to be integrated into the ISE, and I can't for the life of
> me work out how to point it at my simple 9536 design, and waggle a few
> inputs .... Would anyone be able to work though it with me? I'd be happy
> to email them the Orcad ccts and the output files generated by the ISE.
> I think I'd have been OK if I put the design into the integrated
> schematic, but importing EDIFs seems to have confused it, or me.
> Thanks
> David

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