Actually I shouldn't have called them "posted reads". Posting a transaction
means that the initiator never gets an explicit acknowledgement that the
transaction reached its destination (like posting a letter in the mail). PCI
writes are posted. A PCI read by definition is non-posted because the initiator
must receive an acknowledgement (the read data).

What I should have said was that the PCI-X protocol allows the initiator to
pipeline reads. If you have a copy, the PCI-X spec explains it pretty well.
Here's the short version:

In PCI-X, the target of a transaction can terminate the transaction with a split
response, which tells the initiator that the target will get back to him later
with a completion transaction (data if it's a read). The request is tagged with
a 5-bit number that will come back with the completion so that the initiator can
match completions to outstanding requests. The initiator is allowed to have up
to 32 split requests outstanding in the pipeline at any one time. Each read
request can be for up to 4kB of data. The throughput of a system that takes full
advantage of split transaction is highest when the amount of data being
transferred is large and the latency is small enough that 32 tags can keep the
pipeline full.

In PCI, the target of a read transaction must either respond with data
immediately, or repeatedly terminate the read attempts with retry while he goes
off and fetches the data. Once he's fetched it, he will be able to respond
immediately to the initiator on the initiator's next attempt. This is very
inefficient because there is only one transaction in the pipeline at a time. If
the latency is large (the initiator has to retry many times), the throughput is
much lower than when pipelined reads are used.

If PCI-X mode is available, use it. Or, there may be chipset settings that you
can use to improve PCI mode performance. The chipset may be able to do
pre-fetching of data in anticipation of you reading it. There may also be burst
length settings that allow you to increase the amount of data transferred in a
single transaction. You need to read the specs for the chipset you are using and
figure out what can be tweaked.

Mark

Brannon King wrote:
> For those speed tests the device was in PCI mode. I was assuming it would be
> the same speed as PCIX (at the same bus speed) because the timing diagrams
> all looked compatible between the two. Please explain what you mean by "post
> read requests". Is there some workaround for this to make the PCI mode
> handle this better?
>
>