chuk wrote:

> Generating clock delays
>
> I am relatively new to VHDL so pleas excuse me if this is too easy a
> question. I need to be able to generate a time shifted version of the
> clk signal for control purposes in an Xilinx based project. There are
> several options that I have come across:
>
> -Using the after ??n, but this dose not seem to generate any
> difference

Yes, synthesis ignores after statements generally.

> -using the wait until statement though this is not supported by Xilinx
> for some reason

That's basically the same problem as with "after".

> -using the dll (is this the most efficient manor?)

That's the way to go - provided that your FPGA implements
such a circuitry. DLLs are there for exactly such purposes.

> I would like someone to tell me which is the best and most
> controllable manor of generating a clock delay. Thanks

Another alternative is to feed the clock through some normal
circuitry. But you can't describe this in VHDL. Instead, you
need to create a hard-macro that does nothing more than
propagating the signal from input to output. Depending on the
timing information you receive in the data sheets, you can
calculate how often the signal needs to be feed through some
LUTs or other parts.
Although this method is not the very best one, it is working
fine in many cases.

Regards,
Mario