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Old 01-05-2004, 08:35 PM
John_H
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Default Re: is this a good idea

"Paul" <[email protected]> wrote in message
news:[email protected] om...
> "Jerry" <[email protected]> wrote in message

news:<[email protected]>...
> > "Paul" <[email protected]> wrote in message
> > news:[email protected] om...
> > > Hi
> > >
> > > I know that the "reg"'s are all zeroes when powered on (on Xilinx
> > > FPGAs). Is this a good idea (assumption) to work on? Can I assume the
> > > same for ASIC development? that is I don't have to change my codes
> > > later on?
> > >
> > > Thanks.

> >
> > Its the worst idea I have seen on this newsgroup to assume the state of
> > registers at power up in an ASIC.
> > BAD BAD BAD, 300 lashes with a broken O'scope lead for the assumption.
> > Watch your simulator. It should have unknown in registers that were not
> > initialized.
> > Some registers initial state is a don't care, some are very critical, it

all
> > depends on your design.
> >
> > Jer

>
>
> Can't I just tell the foundry that I need the regs to be zeroes at powered

on?
> Anyone done this before?


The foundary would have to use a special register primitive that is
supported by a power-on-reset mechanism added to your circuitry. The ASIC
house would need a different netlist. Do you want them doing some of your
design?

Also - MAJOR caveat: the Xilinx devices do NOT always power up registers to
zero. If the register is implemented with an FDS or FDSE primitive
(synchronous sets) the register powers up to a logic one.

As far as dedicated reset nets, Xilinx has warned many times in the past not
to rely on the dedicated net because the skew across the device - in older
devices, at least - could be large compared to the clock cycle. The
suggestion in another post to synchronize your reset to each clock domain is
superb; releasing reset is usually an asynchronous event that can send only
some of your circuit out of reset on the first clock cycle.

I plan to use the BUFGMUX primitives to bring my FPGA with well-defined
power-on states into operation by enabling the clock to all elements at the
same time rather than rely on an asynchronous power-on reset OR explicit
snchonized resets to each and every friggin register, using significant
routing resources and some logic resources (by eliminating the synchronous
set/reset from my synthesizer's bag of tricks). I would never parlay this
FPGA specific method to an ASIC.


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