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Old 01-05-2004, 06:10 PM
Mark Schellhorn
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Default Re: Xilinx Logicore PCI64 Problem

It sounds like either:

a) You have changed one or more instance names within the design hierarchy so
that the paths 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD' etc. are not valid, or

b) You have allowed the synthesis tool to change the design hierarchy by
flattening or grouping modules.

In my design I used the keep_hierachy XST synthesis attribute to tell XST to
leave the PCI core hierarchy alone when flattening my logic. I also did a
search/replace on the UCF file to change some instance names in the path so that
they match the instance names I wanted to use in my design.

Mark


owner wrote:
> Hi,
>
> I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE
> 4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a.
> NGDBUILD, the design, I encounter the following errors:
>
> ERROR:NgdBuild:393 - Could not find INST(S)
> 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD'
> in design 'gefsc_top'. INST entry is 'INST
> "PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;'
>
> ERROR:NgdBuild:393 - Could not find INST(S)
> 'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD'
> in design 'gefsc_top'. INST entry is 'INST
> "PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;'
>
> ERROR:NgdBuild:393 - Could not find INST(S)
> 'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD'
> in design 'gefsc_top'. INST entry is 'INST
> "PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;'
>
> The error continues for the whole bus width, and for other signals as
> well.
> I think the ucf file specifies the constraints using "/" to reference
> the instance, but the core instantiates in a different way. There is a
> file by the name of "pci_lc_i.vhd" which I found the instance
> PCI_AD64_IO31_OFD instantiated as:
>
> PCI_AD64_IO31_OFD : X_FF
> port map(
> .....
>
> Does this mean I have to change the ucf file's constraint statements?
> Can anyone in the group who has used xilinx logicore pci64 advice me
> on this?
>
> Any help is greatly appreciated.
>
> Regards,
> LC


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