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Old 01-05-2004, 02:25 AM
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Default Re: is this a good idea

"Paul" <[email protected]> wrote in message
news:[email protected] om...
> Hi
> I know that the "reg"'s are all zeroes when powered on (on Xilinx
> FPGAs). Is this a good idea (assumption) to work on? Can I assume the
> same for ASIC development? that is I don't have to change my codes
> later on?
> Thanks.

Its the worst idea I have seen on this newsgroup to assume the state of
registers at power up in an ASIC.
BAD BAD BAD, 300 lashes with a broken O'scope lead for the assumption.
Watch your simulator. It should have unknown in registers that were not
Some registers initial state is a don't care, some are very critical, it all
depends on your design.


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