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Old 01-04-2004, 12:19 PM
Paul
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Default is this a good idea

Hi

I know that the "reg"'s are all zeroes when powered on (on Xilinx
FPGAs). Is this a good idea (assumption) to work on? Can I assume the
same for ASIC development? that is I don't have to change my codes
later on?

Thanks.
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