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Old 12-23-2003, 03:51 PM
Muthu
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Default Re: Net name convention for Xilinx UCF files.

"One Day & A Knight" <[email protected]> wrote in message news:<[email protected]>...
> Hi, all:
>
> I am writing some UCF files for synthesis. In XST I set the hierarchy
> seperator to / and bus symbol to []...
>
> Now after I write the UCF files and build, the ISE6.1 complain can't find
> the net-names.
>
> How do I find the correct names of the various symbols in my Verilog codes?
> Is it possible to write a "netlist" in the NGC files?
>
>
> Best Regards,
> Kelvin
>
>
>
>
> In core.v
> Module main;
>
> testctl u_testctrl(
> ...
> .srck_i(p_srck_i), //testctrl input
>
> .arstn_testrx_i(arstn_testrx), //testctrl input
> .clk36_pll_i(clk_36), //testctrl input
> );
>
> ...
> endmodule
>
> in core_ucf.ucf
> NET "u_testctrl/clk36_pll_o" TNM_NET = "u_testctrl_clk36_pll_o";
> TIMESPEC "TS_u_testctrl_clk36_pll_o" = PERIOD "u_testctrl_clk36_pll_o" 27.8
> ns HIGH 50 %;
>
>
> Error in core.bld
> ERROR:NgdBuild:756 - Line 87 in core_ucf.ucf': Could not find net(s)
> 'u_testctrl/clk36_pll_i' in the design. To suppress this error specify
> the
> correct net name or remove the constraint.


Hi,

Your .ucf having "pll_o" and ERROR shows "pll_i". I think you have
copied wrong lines. thats ok.

XST tools will not change the instance names during synthesis. so,
whatever you type in RTL should be valid in PAR too.

I am doubting, the hiearchy seperator only. Because, XST by default
takes "." as hiearchy seperator. Pls check that again, whether you
have forced correctly to "/"

and you can generate netlist after Translation phase.

it is "ngd2ver" application from Xilinx tools.

Get back for any clarification.

Regards,
Muthu
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