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Old 12-23-2003, 10:19 AM
One Day & A Knight
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Default Net name convention for Xilinx UCF files.

Hi, all:

I am writing some UCF files for synthesis. In XST I set the hierarchy
seperator to / and bus symbol to []...

Now after I write the UCF files and build, the ISE6.1 complain can't find
the net-names.

How do I find the correct names of the various symbols in my Verilog codes?
Is it possible to write a "netlist" in the NGC files?


Best Regards,
Kelvin




In core.v
Module main;

testctl u_testctrl(
...
.srck_i(p_srck_i), //testctrl input

.arstn_testrx_i(arstn_testrx), //testctrl input
.clk36_pll_i(clk_36), //testctrl input
);

....
endmodule

in core_ucf.ucf
NET "u_testctrl/clk36_pll_o" TNM_NET = "u_testctrl_clk36_pll_o";
TIMESPEC "TS_u_testctrl_clk36_pll_o" = PERIOD "u_testctrl_clk36_pll_o" 27.8
ns HIGH 50 %;


Error in core.bld
ERROR:NgdBuild:756 - Line 87 in core_ucf.ucf': Could not find net(s)
'u_testctrl/clk36_pll_i' in the design. To suppress this error specify
the
correct net name or remove the constraint.



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