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Old 11-14-2003, 08:47 PM
Mark van de Belt
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Default Re: Inferring Dual Port Block RAM


"Tom Hawkins" <[email protected]> schreef in bericht
news:[email protected] om...
> Is it possible to infer a dual port block RAM
> when the ports have different memory dimensions?
>
> Say port A has address and data width of 8 and 8,
> while port B has address and data with of 9 and 4,
> for instance.
>
> Instead of using a 2 dimensional array, one could
> define one long array then do appropriate
> bit selection off the 1D array for addressing:
>
> reg [0:2047] memory; // 256x8 or 512x4.
>
> Port A Addressing (pseudo code):
>
> memory[addr_a * 8 : addr_a * 8 + 7]
> // Invalid Verilog, I know.
>
> Port B Addressing:
>
> memory[addr_b * 9 : addr_b * 9 + 3]
>
>
> Or another, more Verilog friendly way, would be to
> use a 2D array with the data as the least common denominator:
>
> reg [3:0] memory [0:512]; // 512x4
>
> Port A Addressing:
>
> {memory[{addr_a, 1b'0}], memory[{addr_a, 1b'1}]}
>
> Port B Addressing:
>
> memory[addr_b]
>
>
> Has anyone had success inferring asymmetric dual-port
> block ram?
>
> -Tom
>
> --
> Tom Hawkins
> Launchbird Design Systems, Inc.
> 952-200-3790
> http://www.launchbird.com/


Hello Tom,

I have created asymmetric blockrams, but always with the aid of library
components or IP cores. I have posted a similar question yesterday for some
VHDL code.

The only problem with the asymmetric blockrams is the translation of the
bits to the addresses on the smaller port. I have found that the LSB's of
the smaller port (port B in your example) must be inverted to get the MSB's
of the port A on the lowest addresses on the B port (MSB of port A first on
the output of port B)

Mark van de Belt


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