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Old 11-13-2003, 10:53 AM
Holger
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Default SystemC Implementation

Hi people, can anybody help me?
I want to implement a clock process in a modul to generate a
independent testbench. My gain is to translate the systemc-code to
vhdl and simulate the projekt in vhdl. It is possible to implement
sc_clock outside sc_main(), but i can not use the parameters for
example sc_clock clk("Clk",20 ,0.5,2,true).

Have anybody a similar problem and have you found a solution?

Thanks.
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