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Old 11-12-2003, 07:34 PM
Jonathan Bromley
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Default Re: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)

"Jan Panteltje" <[email protected]> wrote in message
news:[email protected]

[...]
> So, the 1.4 V pp input video on a CTT pin with 3.3V supply.
> A r2r ladder on the comparator reference.
> A 8 step successive approximation, that looks at 0 / 1 from the input

(video
> lower or higher then reference) gives 8 bit video.


Cool.

[...]
> But this noise, I think maybe the reference or comparator switch level is
> affected by everything else happening in the FPGA?


Random suggestions follow - you've probably thought about
most of these already, but I'll offer them anyway :-)

Do you *know* where the ground reference is that's used for
the output pads that drive your R2R ladder? have you taken
care to use output pads all in the same bank for that?

Could you consider adding a second R2R and digitizing the
video GROUND, also AC coupled in? Then subtract VideoGnd
from VideoHot, add a suitable offset (presumably you're
getting the offset by sampling the back porch somewhere?).
This *might* help if both R2R DACs are driven from buffers
that share a common ground, i.e. are very nearby on the chip.

I've seen 7-bit SNR with very simply constructed R2R DACs
on the output of FPGAs before now, but that was at quite
low frequencies so the FPGA itself would have been much
quieter. I say this because 7-bit should be plenty to get
reasonably quiet-looking video.

Finally, are you sampling a composite NTSC or PAL video
signal? If so, what's happening about aliasing of the
colour subcarrier? Wouldn't it be a good idea to sample
at an exact multiple of Fsc?

Let us know how you progress - it sounds fun.
--
Jonathan Bromley, Consultant

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