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Old 11-11-2003, 06:55 PM
B. Joshua Rosen
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Default Re: Reverse engineering an EDIF file?

On Mon, 10 Nov 2003 23:10:39 +0100, Rastislav Struharik wrote:

> Hello,
>
> I would like to know does anyone knows, is it possible to reverse
> engineer an edif netlist file? I am currently developing an FPGA core.
> I would like to supply an evaluation version of the core, that would
> have all the functionality of the final core, but would operate only
> for a limited period of time. My fear is that there is a way to modify
> the evaluation version edif netlist (find and remove modules that set
> a time limit to the operation of the evaluation version), and thus
> obtain completely functional core. Can something like this be done, or
> am I being paranoid?
> Every help and clarification on this subject is most welcome.
>
> Thanks in advance,
> Rastislav Struharik


You can convert the edif file into Verilog of VHDL by running the Xilinx
programs edif2ngd followed by an ngd2ver or ngd2vhdl. What you get is gate
level so it's not easy to work with but it's at least minimally human
readable.


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