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Old 11-11-2003, 06:10 PM
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Default Re: Reverse engineering an EDIF file?

Dear Allan,

Thank you for your answer. When you say binary format, what precisely
do you mean? On the other hand I was thinking of using Xilinx NGC
netlist instead of EDIF. Do you think this would help? I have read
that NGC is a encrypted netlist format, and if there is no easy way of
converting NGC to EDIF, than maybe it would be a solution to my
problem.

Best regards,
Rastislav

On Tue, 11 Nov 2003 10:45:47 +1100, Allan Herriman
<[email protected]> wrote:

>On Mon, 10 Nov 2003 23:10:39 +0100, Rastislav Struharik
><[email protected]> wrote:
>
>>Hello,
>>
>>I would like to know does anyone knows, is it possible to reverse
>>engineer an edif netlist file? I am currently developing an FPGA core.
>>I would like to supply an evaluation version of the core, that would
>>have all the functionality of the final core, but would operate only
>>for a limited period of time. My fear is that there is a way to modify
>>the evaluation version edif netlist (find and remove modules that set
>>a time limit to the operation of the evaluation version), and thus
>>obtain completely functional core. Can something like this be done, or
>>am I being paranoid?
>>Every help and clarification on this subject is most welcome.

>
>I think you should distribute your design in a binary format, since
>it's fairly easy to reverse engineer EDIF:
>
>Use any text editor for editing.
>
>Use Aldec or Riviera for simulating. (Both tools handle a combined
>VHDL / Verilog / EDIF flow).
>
>Use a recent version of Synplify to convert to (almost readable)
>schematics.
>
>Regards,
>Allan.1


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