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Old 11-08-2003, 06:59 PM
Nate Goldshlag
Posts: n/a
Default Re: latch and shift 15 bits.

In article <[email protected] >, Denis
Gleeson <[email protected]> wrote:

> always @ (ACB_Decade_Count_Enable or OUT_Acquisition_Count or clear)
> if(clear)
> Store_Trigger_Acquisition_Count <= 14'b0;
> else
> begin
> if(ACB_Decade_Count_Enable) // event happened input is high.
> Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
> end

You have a fundamental problem here - the design is not synchrounous.
If ACB_Decade_Count_Enable is a synchronous signal created by your
system clock then you have a race condition here. If
OUT_Acquisition_Count changes before ACB_Decade_Count_Enable goes away,
you may not latch the proper data.

A better way would be the following:

always @(posedge clear or posedge clk)
if (clear)
Store_Trigger_Acquisition_Count <= 15'b0;
if (ACB_Decade_Count_Enable)
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
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