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Old 11-06-2003, 11:53 AM
Denis Gleeson
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Default latch and shift 15 bits.

Hello all

I am trying to implement the following logic in a xilinx XCS05xl
FPGA.

I have a 15 bit binary counter. I need to store its count value
on the occurrence of an event. Some time later I need to shift the stored
counter value out of the FPGA in a serial fashion under the control
of a clock.

What I currently have is:
-----------------------------------------------------------------------
input clear;
reg clear;

input ACB_Decade_Count_Enable;

input ACB_Read_Trigger_Address_Clk;

output ACB_Trigger_Address_Output;
reg ACB_Trigger_Address_Output;

reg [14:0] Store_Trigger_Acquisition_Count; // Storage for counter count.


// Store the count value when ACB_Decade_Count_Enable is high.
always @ (ACB_Decade_Count_Enable)
begin
if(ACB_Decade_Count_Enable) // event happened input is high.
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
end

// Now shift out the stored count serially.
always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk)
begin
if(clear)
begin
ACB_Trigger_Address_Output <=0;
end
else
begin
ACB_Trigger_Address_Output <=Store_Trigger_Acquisition_Count[14];
Store_Trigger_Acquisition_Count <= Store_Trigger_Acquisition_Count << 1;
end
end

-----------------------------------------------------------------------

With this code my synthesis step gives the following errors.

Warning - Latch inferred in design "My block" read with
'hdlin_check_no_latch'(HDL - 307)

Error - The net /../my block/Store_Trigger_Acquisition_Count<13> has more
than one driver(FPGA-CHECK-5)

The last error is repeated for all bits in Store_Trigger_Acquisition_Count.


The logic above seems correct in my head but Im not an FPGA expert.
Obviously I need a different implementation. Any suggestions.


Many thanks for all suggestions in advance.

Denis
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