ISE : Synthesis process hangs
We are trying to implement a decoder design on a Spartan II(2s200), and when I run the Synthesize process, the message window shows that all verilog modules are being compiled, however the process seems to take forever when it is trying the compile the unisim_comp.v file which is provided by ISE.
Can anybody guess what the problem could be and/or the possible solution.
Thanks in advance
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