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Old 10-01-2003, 01:22 AM
Kenneth Land
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Default Re: USB 1.1/2.0 Implementation


So, when you plugin your device, does Windows say New Device Found, etc.?
Giving you a chance to install a driver? If so, does it tell you the name
of the device?

I"ve never built our driver, but I'll give it the ol' 15 minute try.

Ken

"SneakerNet" <[email protected]> wrote in message
news:[email protected]
> Hi Ken
>
> Thanks for the important tip. I'll give that a shot. (so there is no way u
> can send me driver? all i need is a driver with vendor id = 0c91 and

product
> id = 2001).
> Anyway like u mentioned, very big pity that the guys didn't include

drivers
> and they gave their whole vhdl code free. Pity!
>
> Hope god has mercy on my soul while i'm doing usb driver.. LOL
> Thanks Ken
> Kind Regards
>
>
>
> "Ken Land" <[email protected]> wrote in message
> news:[email protected]
> > Hey Sneaker,
> >
> > I can't give you the code to our host side driver (I don't own it) but I

> can
> > tell you its a slight modification to a sample driver in the MicroSoft
> > Device Driver Kit.
> >
> > From the original header. (So you could search)
> >
> > Copyright (c) 1995 Microsoft Corporation
> > Module Name:
> > I82930.c
> > Abstract:
> > USB device driver for Intel 82930 USB test board
> > Environment:
> > kernel mode only
> >
> > So if you have access to or can get the MS DDK then I think it has all

you
> > need.
> > Our setup was pretty much done for us, but you need to compile this

driver
> > with a unique filename and maybe your USB ID (not sure about this) and

> then
> > you setup a .inf file that says your device uses this driver file.
> > (executable renamed to SneakersUSB.SYS or such)
> >
> > "your device" is the name that should show up even without a driver when

> you
> > plug it into a Windows box. I assume the USB core has some default.

(.inf
> > file basically maps this name to which driver to load. May be able to

use
> > someone elses driver by creating a .inf for all I know)
> >
> > Surprised they gave away the core, but not the driver they tested it

with.
> >
> > Good Luck!
> > Ken
> >
> >
> >
> >
> > "SneakerNet" <[email protected]> wrote in message
> > news:[email protected]
> > > Hello again Paul ;o)
> > >
> > > LOL, tell you what, I already cracked it. I found that document

sometime
> > > back now *grins*.
> > > And I also cracked that the CLKDLL is just a pll *grins again* and

thus
> I
> > > had posted another msg (which you have already replied before) but

once
> > > again I beat you to it. I cracked it before you replied ;o).
> > >
> > > Anyway thanks for taking time in explaning the Xilinx components.
> > > Regarding the free USB Cores from Altera website.
> > > Service I would give umm 10% *no offence*. I had to log into that page

> and
> > > request the core nearly 10 times before someone contacted me from

> Altera.
> > > Then after 2-3 days they told me that USB 2.0 core is not functional

so
> i
> > > asked for usb 1.1 core. Then they asked me hundreds of questions of

> > why/what
> > > for/how long etc etc. When I finally got it, it was only licenced for

a
> > > month (which passes by just like that as I'm working on this USB

project
> > > part time.
> > > Anyway I found a site that had the full VHDL USB core free of cost

> > (without
> > > any need for any hardware). I'm stuck at the windows driver now. Rest

is
> > all
> > > ready to go..
> > >
> > > Any help on how to install a generic usb driver?
> > >
> > > Thanks for your response Paul.
> > > Bye
> > >
> > > "Paul Leventis" <[email protected]> wrote in message
> > > news:[email protected] able.rogers.com...
> > > > Hi SneakerNet,
> > > >
> > > > I just noticed we have VERY handy application note for you -- AN307
> > > > (available on www.altera.com) describes how to migrate from a Xilinx
> > > design
> > > > to an Altera design. There is a section dedicated to DLL to PLL
> > > conversion
> > > > that should be able to help you out. Below is my attempt at

> explaining
> > > > things before I found this app note.
> > > >
> > > > In Altera's FPGAs, we've got PLLs, which provide a superset of the

> > CLKDLL
> > > > function you're trying to use. You'd want to setup your PLL to use

> > CLKIN
> > > as
> > > > its input inclk0, hook up the C0 port to GCLK signal and C1 port to

> CLK
> > > > signal, don't apply any phase shift, and use the C0 port to

compensate
> > the
> > > > PLL output. Connect RST to the areset port, and LOCKED to the

locked
> > > port.
> > > > You'll want to setup your C1 port to have a 2x frequency multiplier

on
> > it.
> > > > The Lock and Reset signals have some sort of equivalent that I can't
> > > recall.
> > > > You can do this all through the allpll megafunction.
> > > >
> > > > The BUFGs are not necessary in Altera parts. In Xilinx parts, these
> > > buffers
> > > > are needed to explicitly indicate that you want a signal to be

driven
> > onto
> > > > the global clock network. Quartus allows you to make "global"

> > assignments
> > > > to nets, but it automatically promotes anything it finds that looks

> like
> > a
> > > > clock net, as well as high-fanout or asynchronous signals if there

are
> > > > enough global clocks available. The PLL output nets will be

> > automatically
> > > > promoted to global clock nets for you, and the PLL input will be

> > assigned
> > > to
> > > > the associated input clock pin.
> > > >
> > > > Also, I should point out that there are four USB cores listed on our
> > > > Intellectual Property page (www.altera.com) under Interfaces &

> > Peripherals
> > > > under USB. All are available for free trial under our OpenCore

> > evaluation
> > > > program.
> > > >
> > > > Regards,
> > > >
> > > > Paul Leventis
> > > > Altera Corp.
> > > >
> > > >
> > > > "SneakerNet" <[email protected]> wrote in message
> > > > news:[email protected]
> > > > > Hi Antti
> > > > > Thanks for the response.
> > > > > haha. I don't expect anyone to do work for me, othwersie I won't

> learn
> > > > > anything, but I wouldn't mind some guidance along the way from you
> > > guys..
> > > > > Anyway I need to ask 2 questions regarding your reply.
> > > > > 1. When you say USB11T11A, do you mean the Philips tranceiver
> > > PDIUSBP11A?
> > > > If
> > > > > no then I'm sorry but i'm not able to find anything on USB11T11A.

> Have
> > I
> > > > > gone blind?
> > > > > 2. Regarding the usb (japanese design), I have ended up towards a

> > brick
> > > > > wall. What I mean to say is, I have been looking at the design for
> > > couple
> > > > of
> > > > > hours and there are 4 components that I'm not sure what they do.

The
> > > main
> > > > > problem is that the code was written for a Xilinx component and

> > because
> > > > I'm
> > > > > using Altera component, I'm do not have the librabires that these
> > > > component
> > > > > are using.
> > > > > Firstly the library defined is (which is for Xilinx only (pls

> correct
> > me
> > > > if
> > > > > i'm wrong))
> > > > > library unisim;
> > > > > use unisim.vcomponents.all;
> > > > >
> > > > > and the 4 components that are using this library are
> > > > > u_DLL : CLKDLL
> > > > > port map ( CLKIN => CLKINM,
> > > > > CLKFB => GCLK,
> > > > > RST => RST,
> > > > > CLK0 => GCLKM,
> > > > > CLK2X => CLKM,
> > > > > LOCKED => LOCK
> > > > > );
> > > > >
> > > > > u_GCLK : BUFG
> > > > > port map ( I => GCLKM,
> > > > > O => GCLK
> > > > > );
> > > > >
> > > > > u_CLK : BUFG
> > > > > port map ( I => CLKM,
> > > > > O => CLK
> > > > > );
> > > > >
> > > > > u_CLKIN : IBUFG
> > > > > port map ( I => CLKIN,
> > > > > O => CLKINM
> > > > > );
> > > > >
> > > > > If you can explain me how I can replace these components for

Altera
> > > > design,
> > > > > I will have a step to progress. If I can get past this point, then

I
> > > have
> > > > > something to try on the chip and play around. My problem is that

> right
> > > now
> > > > I
> > > > > can't go past compiling as Quartus doesn't recognize these

> components
> > > (or
> > > > > the library). Pls Advice
> > > > >
> > > > > Thanks again
> > > > >
> > > > > Regards
> > > > >
> > > > >
> > > > > "Antti Lukats" <[email protected]> wrote in message
> > > > > news:[email protected] om...
> > > > > > "SneakerNet" <[email protected]> wrote in message

> news:<p43cb.157047
> > > > > > > Has anyone successfully implemented USB 2.0 or USB 1.1

protocol
> in
> > > > > > [deleted]
> > > > > >
> > > > > > USB11T11A FS/LS USB tranceiver
> > > > > >
> > > > > > usb_phy (opencores) UTMI interface that connects to USB11T11A
> > > > > >
> > > > > > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > > > > > USB11T1A it is not HID but it will enumerate in hardware iw the

> USB
> > > > > > host will 'see' it, but ther is no host software provide
> > > > > >
> > > > > > usb (japanase desing) full HID USB core includes USB11T1A model)

> can
> > > > > > directly be connected to usb D+ D- pins! (no tranceiver chip),

> there
> > > > > > is some VB test program to talk to the core (as it is HID

> > peripheral)
> > > > > >
> > > > > > antti
> > > > > > PS I am afraid you have todo some homework cant do it for you
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >

> >
> >

>
>



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