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Old 09-30-2003, 05:49 AM
Paul Leventis
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Posts: n/a
Default Re: USB 1.1/2.0 Implementation

Hi,

Well, serves me right for going away... all my posts are for naught :-)

One small correction: DLLs are *not* PLLs -- though their first-order
behaviour seems similar. They are fundamentally different approaches to
solving the same problem. DLLs pass an input clock through a programmable
delay chain, and adjusts delay until the edges of the output clock and input
clock align. PLLs synthesize a clock via a VCO and phase shift the
resulting clock relative to the input clock. This means high-frequency
jitter on the input is filtered out in a PLL, but transmitted in a DLL.
PLLs usually have better clock frequency synthesis options, as they can
include multiply/divide counters in their feedback loop; DLLs can provide
some such capabilities via digital hardware, but it is very limited. There
are other differences between the two in how they respond to low- and
high-frequency jitter/drift, their noise susceptibility, range of operation
in input/output frequencies, granularity of phase/frequency adjustment,
response to temperature/voltage variation, and numerous other areas that I
can't recall precisely. Which is better depends on your application, though
generally speaking PLLs provide a more versatile solution.

Obviously we at Altera feel that PLLs are the better choice for our users,
as this is what we have chosen to build on all of our devices since APEX.
Stratix includes up to 12 PLLs of various flavours.

I can't help you on the device driver front.

I'll pass on your comes re: usb core availability and your experience with
the web to the appropriate groups.

Regards,

Paul Leventis
Altera Corp.


"SneakerNet" <[email protected]> wrote in message
news:[email protected]
> Hello again Paul ;o)
>
> LOL, tell you what, I already cracked it. I found that document sometime
> back now *grins*.
> And I also cracked that the CLKDLL is just a pll *grins again* and thus I
> had posted another msg (which you have already replied before) but once
> again I beat you to it. I cracked it before you replied ;o).
>
> Anyway thanks for taking time in explaning the Xilinx components.
> Regarding the free USB Cores from Altera website.
> Service I would give umm 10% *no offence*. I had to log into that page and
> request the core nearly 10 times before someone contacted me from Altera.
> Then after 2-3 days they told me that USB 2.0 core is not functional so i
> asked for usb 1.1 core. Then they asked me hundreds of questions of

why/what
> for/how long etc etc. When I finally got it, it was only licenced for a
> month (which passes by just like that as I'm working on this USB project
> part time.
> Anyway I found a site that had the full VHDL USB core free of cost

(without
> any need for any hardware). I'm stuck at the windows driver now. Rest is

all
> ready to go..
>
> Any help on how to install a generic usb driver?
>
> Thanks for your response Paul.
> Bye
>
> "Paul Leventis" <[email protected]> wrote in message
> news:[email protected] able.rogers.com...
> > Hi SneakerNet,
> >
> > I just noticed we have VERY handy application note for you -- AN307
> > (available on www.altera.com) describes how to migrate from a Xilinx

> design
> > to an Altera design. There is a section dedicated to DLL to PLL

> conversion
> > that should be able to help you out. Below is my attempt at explaining
> > things before I found this app note.
> >
> > In Altera's FPGAs, we've got PLLs, which provide a superset of the

CLKDLL
> > function you're trying to use. You'd want to setup your PLL to use

CLKIN
> as
> > its input inclk0, hook up the C0 port to GCLK signal and C1 port to CLK
> > signal, don't apply any phase shift, and use the C0 port to compensate

the
> > PLL output. Connect RST to the areset port, and LOCKED to the locked

> port.
> > You'll want to setup your C1 port to have a 2x frequency multiplier on

it.
> > The Lock and Reset signals have some sort of equivalent that I can't

> recall.
> > You can do this all through the allpll megafunction.
> >
> > The BUFGs are not necessary in Altera parts. In Xilinx parts, these

> buffers
> > are needed to explicitly indicate that you want a signal to be driven

onto
> > the global clock network. Quartus allows you to make "global"

assignments
> > to nets, but it automatically promotes anything it finds that looks like

a
> > clock net, as well as high-fanout or asynchronous signals if there are
> > enough global clocks available. The PLL output nets will be

automatically
> > promoted to global clock nets for you, and the PLL input will be

assigned
> to
> > the associated input clock pin.
> >
> > Also, I should point out that there are four USB cores listed on our
> > Intellectual Property page (www.altera.com) under Interfaces &

Peripherals
> > under USB. All are available for free trial under our OpenCore

evaluation
> > program.
> >
> > Regards,
> >
> > Paul Leventis
> > Altera Corp.
> >
> >
> > "SneakerNet" <[email protected]> wrote in message
> > news:[email protected]
> > > Hi Antti
> > > Thanks for the response.
> > > haha. I don't expect anyone to do work for me, othwersie I won't learn
> > > anything, but I wouldn't mind some guidance along the way from you

> guys..
> > > Anyway I need to ask 2 questions regarding your reply.
> > > 1. When you say USB11T11A, do you mean the Philips tranceiver

> PDIUSBP11A?
> > If
> > > no then I'm sorry but i'm not able to find anything on USB11T11A. Have

I
> > > gone blind?
> > > 2. Regarding the usb (japanese design), I have ended up towards a

brick
> > > wall. What I mean to say is, I have been looking at the design for

> couple
> > of
> > > hours and there are 4 components that I'm not sure what they do. The

> main
> > > problem is that the code was written for a Xilinx component and

because
> > I'm
> > > using Altera component, I'm do not have the librabires that these

> > component
> > > are using.
> > > Firstly the library defined is (which is for Xilinx only (pls correct

me
> > if
> > > i'm wrong))
> > > library unisim;
> > > use unisim.vcomponents.all;
> > >
> > > and the 4 components that are using this library are
> > > u_DLL : CLKDLL
> > > port map ( CLKIN => CLKINM,
> > > CLKFB => GCLK,
> > > RST => RST,
> > > CLK0 => GCLKM,
> > > CLK2X => CLKM,
> > > LOCKED => LOCK
> > > );
> > >
> > > u_GCLK : BUFG
> > > port map ( I => GCLKM,
> > > O => GCLK
> > > );
> > >
> > > u_CLK : BUFG
> > > port map ( I => CLKM,
> > > O => CLK
> > > );
> > >
> > > u_CLKIN : IBUFG
> > > port map ( I => CLKIN,
> > > O => CLKINM
> > > );
> > >
> > > If you can explain me how I can replace these components for Altera

> > design,
> > > I will have a step to progress. If I can get past this point, then I

> have
> > > something to try on the chip and play around. My problem is that right

> now
> > I
> > > can't go past compiling as Quartus doesn't recognize these components

> (or
> > > the library). Pls Advice
> > >
> > > Thanks again
> > >
> > > Regards
> > >
> > >
> > > "Antti Lukats" <[email protected]> wrote in message
> > > news:[email protected] om...
> > > > "SneakerNet" <[email protected]> wrote in message news:<p43cb.157047
> > > > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
> > > > [deleted]
> > > >
> > > > USB11T11A FS/LS USB tranceiver
> > > >
> > > > usb_phy (opencores) UTMI interface that connects to USB11T11A
> > > >
> > > > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > > > USB11T1A it is not HID but it will enumerate in hardware iw the USB
> > > > host will 'see' it, but ther is no host software provide
> > > >
> > > > usb (japanase desing) full HID USB core includes USB11T1A model) can
> > > > directly be connected to usb D+ D- pins! (no tranceiver chip), there
> > > > is some VB test program to talk to the core (as it is HID

peripheral)
> > > >
> > > > antti
> > > > PS I am afraid you have todo some homework cant do it for you
> > >
> > >

> >
> >

>
>



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