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Old 09-25-2003, 03:22 AM
rickman
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Default Re: USB 1.1/2.0 Implementation

SneakerNet wrote:
>
> Hi Antti
> Thanks for the response.
> haha. I don't expect anyone to do work for me, othwersie I won't learn
> anything, but I wouldn't mind some guidance along the way from you guys..
> Anyway I need to ask 2 questions regarding your reply.
> 1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A? If
> no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
> gone blind?
> 2. Regarding the usb (japanese design), I have ended up towards a brick
> wall. What I mean to say is, I have been looking at the design for couple of
> hours and there are 4 components that I'm not sure what they do. The main
> problem is that the code was written for a Xilinx component and because I'm
> using Altera component, I'm do not have the librabires that these component
> are using.
> Firstly the library defined is (which is for Xilinx only (pls correct me if
> i'm wrong))
> library unisim;
> use unisim.vcomponents.all;
>
> and the 4 components that are using this library are
> u_DLL : CLKDLL
> port map ( CLKIN => CLKINM,
> CLKFB => GCLK,
> RST => RST,
> CLK0 => GCLKM,
> CLK2X => CLKM,
> LOCKED => LOCK
> );
>
> u_GCLK : BUFG
> port map ( I => GCLKM,
> O => GCLK
> );
>
> u_CLK : BUFG
> port map ( I => CLKM,
> O => CLK
> );
>
> u_CLKIN : IBUFG
> port map ( I => CLKIN,
> O => CLKINM
> );
>
> If you can explain me how I can replace these components for Altera design,
> I will have a step to progress. If I can get past this point, then I have
> something to try on the chip and play around. My problem is that right now I
> can't go past compiling as Quartus doesn't recognize these components (or
> the library). Pls Advice


This is something I know a bit more about. These are all clock
components. CLKDLL is a DLL (Delay Locked Loop) like a PLL only more
Xilinx like The Altera parts have PLLs depending on the part. I
don't know if this is required or just used to allow different external
and internal clock rates.

The BUFG and IBUFG are just clock buffers. They are used to drive the
internal clock distribution networks. Altera should have equivalent
components or you may not need to instantiate them since they are
typically locked to a given pin and should be inferred by most tools.
Read up a bit on the Xilinx and Altera chips and this will all be very
clear.

--

Rick "rickman" Collins

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