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Old 09-24-2003, 10:38 PM
SneakerNet
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Default Re: USB 1.1/2.0 Implementation

Hi Antti
Thanks for the response.
haha. I don't expect anyone to do work for me, othwersie I won't learn
anything, but I wouldn't mind some guidance along the way from you guys..
Anyway I need to ask 2 questions regarding your reply.
1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A? If
no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
gone blind?
2. Regarding the usb (japanese design), I have ended up towards a brick
wall. What I mean to say is, I have been looking at the design for couple of
hours and there are 4 components that I'm not sure what they do. The main
problem is that the code was written for a Xilinx component and because I'm
using Altera component, I'm do not have the librabires that these component
are using.
Firstly the library defined is (which is for Xilinx only (pls correct me if
i'm wrong))
library unisim;
use unisim.vcomponents.all;

and the 4 components that are using this library are
u_DLL : CLKDLL
port map ( CLKIN => CLKINM,
CLKFB => GCLK,
RST => RST,
CLK0 => GCLKM,
CLK2X => CLKM,
LOCKED => LOCK
);

u_GCLK : BUFG
port map ( I => GCLKM,
O => GCLK
);

u_CLK : BUFG
port map ( I => CLKM,
O => CLK
);

u_CLKIN : IBUFG
port map ( I => CLKIN,
O => CLKINM
);

If you can explain me how I can replace these components for Altera design,
I will have a step to progress. If I can get past this point, then I have
something to try on the chip and play around. My problem is that right now I
can't go past compiling as Quartus doesn't recognize these components (or
the library). Pls Advice

Thanks again

Regards


"Antti Lukats" <[email protected]> wrote in message
news:80a3aea5.030924011[email protected] om...
> "SneakerNet" <[email protected]> wrote in message news:<p43cb.157047
> > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in

> [deleted]
>
> USB11T11A FS/LS USB tranceiver
>
> usb_phy (opencores) UTMI interface that connects to USB11T11A
>
> usb1.1 (opencores) connects to usb_phy (opencores) connects to
> USB11T1A it is not HID but it will enumerate in hardware iw the USB
> host will 'see' it, but ther is no host software provide
>
> usb (japanase desing) full HID USB core includes USB11T1A model) can
> directly be connected to usb D+ D- pins! (no tranceiver chip), there
> is some VB test program to talk to the core (as it is HID peripheral)
>
> antti
> PS I am afraid you have todo some homework cant do it for you



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