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Old 09-24-2003, 04:32 AM
SneakerNet
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Default Re: USB 1.1/2.0 Implementation


"rickman" <[email protected]> wrote in message
news:[email protected]
> SneakerNet wrote:
> >
> > "Antti Lukats" <[email protected]> wrote in message
> > news:[email protected] om...
> > > "SneakerNet" <[email protected]> wrote in message

> > news:<[email protected]>...
> > > > Hi All
> > > >
> > > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in

> > Altera
> > > > Device. If yes, can you pls start me off. I'm not able to make any

> > progress
> > > > in this. I have found couple of sites in ths area, but always end

> > towards a
> > > > brick wall.
> > >
> > > if you dont say what your problem is how could one help?
> > > the USB cores available are working out of box for Xilinx, for altera
> > > you need to change the technology dependant portions and it should
> > > again work.
> > >
> > > antti

> >
> > Hi Antti
> > Thanks for the response. I actually contacted you regarding USB page

that
> > you mentioned in this newsgroup a while back (Japanese language).
> > Ok firstly regarding USB implementation, the way I see it, there are 3

major
> > parts, which are:
> > 1. USB Transceiver (to connect the FPGA and the PC)
> > 2. FPGA Implementation
> > 3. Windows App
> >
> > Now
> > 1. USB Transceiver - I have found out that the Philips PDIUSBP11A is

quite
> > suitable for this job. However if you look at this pdf (which shows the
> > circuit connection) www.semiconductors.philips.com/acrobat/
> > applicationnotes/AN10007-01.pdf , on page 5 of this pdf there are 2

circuit
> > diagrams. I'm not able to understand the difference between upstream and
> > downstream circuits. Pls help/advice.

>
> I have not looked at the circuits, but upstream is closer to the PC and
> so is a "host" type connection while downstream is closer to (or is) the
> peripheral. I think there are only very small differences having to do
> with initialization protocol.


Thanks for the clarification.

>
>
> > 2. FPGA Implementation - Antti, you replyed saying (for altera you need

to
> > change the technology dependant portions and it should again work.).

What do
> > you mean by this? Help Again. Where can I download the USB cores to

begin
> > with? Once I can get hold of the USB core, I guess I'll have a starting
> > point.

>
> I think he was saying that he is aware of IP that works in the Xilinx
> chips and so would work in any other FPGA. But the coding style may
> have used chip specific features (like the 16 bit SRL in the Xilinx
> parts). If so, this code may need to be changed to something more
> generic for an Altera part. Any Xilinx features that are instantiated
> will need to be replaced for sure.
>
> Check www.opencores.org. They have USB 1.1 and 2.0 implementations
> available. I don't know if they are vendor specific or not.
>


Err.. I found this usb_phy from opencores.org however I'm struggling with
that. The main top layer file has so many I/O's compared to the I/Os of the
PDIUSBP11A, i'm stuck. I'm stuck in the sense that I do not know which pin
will map which one on the transcevier.

>
> > 3. Windows Implementation - I have no clue with regards to windows

drivers.
> > Any help in this matter would be very greatful.

>
> This depends on your application. I believe there is a generic set of
> drivers to support a "human interface device" or similar which means it
> works like a mouse or keyboard in terms of sending data in small
> packets.
>
> Again, I am not directly experienced with this, but I have been
> listening intently when others discuss this here and elsewhere.


Sigh.. I guess I'll join you ..

Thanks for your input.

>
> --
>
> Rick "rickman" Collins
>
> [email protected]
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
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