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Old 12-04-2007, 11:59 PM
Mike Treseler
Posts: n/a
Default Re: Post Synthesis and Post Place/Rout Simulation

[email protected] wrote:

> Question is "How to correctly point to gate-level sim files"?

After the functional testbench sims ok (step 1)
compile the gate module over the rtl using the
same name, and sim again. If everything
lines up ok, expect the same answer,
but it will take longer.

-- Mike Treseler
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