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Old 12-04-2007, 10:32 PM
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Default Post Synthesis and Post Place/Rout Simulation


For: Aldec Riviera-PRO 2007.10 and Active_HDL 7.2.

Does anyone have an example simulation .do file for Post Synthesis and
Post Place/Rout Simulation.

Question is "How to correctly point to gate-level sim files"?

Thanks.
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