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Old 07-26-2007, 08:38 PM
Posts: n/a
Default Re: variable clock frequency generation issue

On Jul 25, 4:45 pm, Chris Briggs <[email protected]> wrote:
> SB wrote:
> > I am working with a verilog behavioral model of a variable frequency
> > clock.
> > The model has two parts. The first part, through a series of case
> > statements selects the period
> > of the output clock signal. The second part of the model the
> > generates
> > the clock signal using the newly defined clock period.

> > Hence the second part looks similar to:
> > always
> > begin
> > #(half_period) clk_sig <= ~clk_sig;
> > end

> Has nothing to do with it being a real value. Has to do with that
> thread blocking on a # delay and you can't change it while it's
> waiting. However, you can abort it using disable. After the begin-end
> is disabled, the always will restart it and it will use the new
> half_period. Note: disable is non-synthesizable, but then, so are #
> delays.
> First, label the clock generator block, as in:
> always begin : clock_gen
> #(half_period) clk_sig = ~clk_sig;
> end
> And then, whenever half_period is updated, disable the block, as in:
> always @(half_period)
> disable clock_gen;
> Alternatively, you could just add 'disable clock_gen;' after the
> line(s) that changes half_period.
> Also, as the other poster mentioned, there's usually no reason to use
> a nonblocking assign in a clock generator.
> -cb

Hi All,

I tried the method of labelling the always block and then
aborting the wait time with a disable command when the new
half_period has been defined. The labelled always
block then picks up the new half_period value and it
progresses properly. This has worked for the
preliminary testing so far. I will test this with further
values going forward and update soon if there are any further

Thank you to everyone for taking an interest in this.


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